1. Field of the Invention
The present invention concerns a semiconductor device for reading various control parameter information stored in an information storage portion such as a fuse and a controlling method therefor. It particularly relates to a semiconductor device capable of reliably reading control parameter information from an information storage portion and keeping the same in an internal circuit upon turning-ON of a power source, as well as a controlling method thereof.
2. Description of the Related Art
In a semiconductor device, by properly cutting a fuse provided in a fuse circuit disposed in the device, redundant address information, operation specification information, etc. are stored. Such pieces of information are read into the internal circuit and held upon turning-ON of a power source and supplied to a circuit to be controlled. For example, a fuse circuit 100 disclosed in Japanese Patent Application No. 2001-354402 as a prior application filed by the present applicant (FIG. 6) comprises a fuse portion 120, a transfer portion 130 and a holding portion 140.
In the fuse portion 120, fuse information is read by control signals INA, INB, and INC. A fuse 112 is connected between a node 103 and a node 104 a PMOS transistor 110 is connected between the node 103 and a power source voltage VDD. An NMOS transistor 114 is connected between the node 104 and a ground voltage VSS. An NMOS transistor 116 is connected between the node 103 and the ground voltage VSS. Then, the control signals IN, INB, and INC are generated in a power source detection circuit (not illustrated) based on a power-ON reset signal POR (not illustrated) for detecting the rise of the power source voltage VDD. The power-ON reset signal POR is a pulse signal having a pulse width of a first period (P1) and the control signals INA, INB, and INC are outputted in accordance with the pulse signal (refer to FIG. 7).
In the first period (P1) in FIG. 7, the control signal INA is at the ground voltage level upon rise of the power-ON reset signal POR (not illustrate). The PMOS transistor 110 turns ON for the first period (P1) being controlled by the control signal INA to connect the node 103 with the power source voltage VDD. The NMOS transistor 114 turns ON before and after the first period (P1) being controlled by the control signal INC which is a signal cophasal with the control signal INA and turns OFF for the first period (P1).
In a case where the fuse is not fused, the voltage level at the node 104 is at the voltage level of the power source voltage VDD by the turning-ON of the PMOS transistor 110. After the completion of the first period (P1), the voltage level at the node 103 and the node 104 is fixed to the voltage level of the ground voltage VSS by the NMOS transistor 114 and the NMOS transistor 116 that turns ON with a delay by the control signal INB.
In a case where the fuse is fused, the voltage level at the node 103 is not transmitted to the node 104 even when the PMOS transistor 110 turns ON. Accordingly, the voltage at the node 104 is kept at the voltage level of the ground voltage VSS.
The transfer portion 130 transfers the fuse information from the fuse portion 120 to the holding portion 140 by the control signal IND. A transfer gate 118 is connected between the node 104 and the node 105 and turns ON in the former half of the first period (P1) and turns OFF in the latter half of the first period (P1) by the control signal IND,/IND. During the ON-period of the transfer gate 118, the voltage level at the node 104 is transmitted to the node 105.
The holding portion 140 holds the fuse information transferred by the transfer portion 130 and outputs it as fuse signal FUSE. A high level is outputted in a case where the fuse is not fused, while a low level is outputted in a case where it is fused.
FIG. 8 shows a semiconductor device disclosed in Patent Document 1. An input signal from each of input terminals is judged by an NAND gate 203, an inverter gate 204, and an NOR gate 205, and is outputted from a flip-flop circuit 206 as a mode register set signal MRS in accordance with a clock signal MCLK. The mode register set signal MRS is inverted by an inverter gate 208 and inputted as a set signal SET to a fuse circuit 200.
The fuse circuit 200 comprises a fuse portion 220 and a holding portion 221. In the fuse portion 220, a fuse 212 is connected between a node 216 and a node 217. A PMOS transistor 210 is connected between the node 216 and a power source voltage VDD. An NMOS transistor 211 is connected between the node 217 and a ground voltage VSS. The holding portion 221 comprises an inverter gate 215 and a PMOS transistor 214 and is connected with the node 216. The voltage level at the node 216 is inverted and held in the holding portion 221 to output a fuse signal FUSE in accordance with the voltage level at the fuse 212.
FIG. 9 shows a timing chart. At a clock cycle E1, a mode register set signals MRS is actuated by a mode register set command (MRS) to activate a set signal SET. Then, at a clock cyclic E2, the mode resistor set signal MRS is inactivated by an autorefresh command (AREF) to inactuate the set signal SET. The PMOS transistor 210 in the fuse portion 220 is controlled by the set signal SET, and turns ON in a period from clock cycles E1 to E2. Further, the NMOS transistor 211 is controlled in the same manner by the set signal SET, turns OFF in the period for the clock cycles E1 to E2 and turns ON before and after thereof.
In a case where the fuse 212 is not fused, while the voltage level at the node 216 takes a high level by the turning-ON of the PMOS transistor 210 at the clock cycle El, but takes a low level by the turning-ON of the NMOS transistor 211 in the clock cycle E2.
In a case where the fuse 213 is not fused, the MOS transistor turns ON to a high level in the clock cycle E1. However, in the clock cycle E2, since the fuse 212 is fused, the node 216 keeps the high level even when the NMOS transistor 211 turns ON.
In the holding portion 221, after the clock cycle E2, fuse information is held in accordance with the state of the fuse 212 to output a fuse signal FUSE.
Other relevant technique includes a fuse circuit disclosed in Patent Document 2. It comprises a structure in which the fuse circuit is divided into two groups and the operation timing is deviated between the groups. However, the group that operates at first is actuated in the same manner as in Japanese Patent Application No. 2001-354402 or the Patent Document 1 described above.
The prior art documents described above are as shown below.
Patent Document 1: U.S. Pat. No. 6,084,803 Specification
Patent Document 2: JP-A No. 2002-175696
In Japanese Patent Application No. 2001-354402 as the prior application of the present applicant, the signals INA, INB, INC, IND,/IND are generated based on the power-ON reset signal POR. Generally, a power source detection circuit for generating the power-ON reset signal POR is provided by one to a predetermined place of a device. On the other hand, the fuse circuit 100 is sometimes arranged being scattered to appropriate places on the device for handling versatile information such as device redundant address information, operation specification information, etc. FIG. 10 shows the state. Fuse circuits 402A, 402B, and 402C are arranged to respective positions to a power source detection circuit 401. Accordingly, the parasitic loads on the signal line 404 from the power source detection circuit 401 to the fuse circuits 402A, 402B, and 402C are different respectively. In the same manner, the parasitic loads on the power source line 405 from the power source 403 to each of the fuse circuits 402A, 402B, and 402C are different respectively. Further, taking notice on one fuse circuit (for example, 402A), the signal line 404 from the power detection circuit 401 and the power source line 405 from the power source 403 may sometimes have the parasitic load different from each other.
Therefore, it may be considered that deviation is caused for the propagation speeds of signals INA, IBN, INC, IND,/IND depending on the parasitic capacitance of the signal line 404, and the margin for the transition timing between the signals may be lost. A correct circuit operation can not possibly be obtained to bring about a problem.
Further, in each of the fuse circuits 402A, 402B, and 402C, the time constant for the rising of the power source voltage supplied by way of the power source line 405 and the propagation time constant of the signals INA, IBN, INC, IND,/IND transmitted by way of the signal line 404 may sometimes be different from each other. In a case where the signals INA, IBN, INC, IND,/IND are transmitted in a state where no sufficient voltage level is supplied as the power source voltage, it may be a possibility that the level of the transmitted signal can not be correctly recognized, or a possibility that no correct output result can be obtained due to slow circuit operation, which brings about a problem.
In Patent Document 1, a problem exists in a case where the first command after the turning-ON of the power source is a command different from an initialization command of the device such as a mode register set command. For example, in a case of a write command, it is necessary to refer to a fuse information necessary for the writing operation. Accordingly, it is required to delay the operation of an internal circuit for a time till the fuse information is defined, which may possibly degrade the high speed operation performance to bring about a problem.
Further, in a case where a read command is inputted succeeding to the first command, after the turn ON of the power source, the fuse information necessary for the read operation is defined at the start of the read command. The fuse information may be inverted by the power source noise, etc. accompanying the first command operation before definition of the fuse information to possibly define an erroneous fuse information which brings about a problem.
The present invention has been achieved in order to solve at least one of the problems in the prior art. That is, it intends to provide a semiconductor device capable of reliably reading control parameter information from the information storage portion and hold the same in the internal circuit upon turning-ON of the power source, as well as a control method thereof.